The use of MOS floating gate storage devices in semiconductor memories has increased rapidly in recent years. A typical MOS floating gate storage device includes a floating gate structure disposed over the surface of a semiconductor substrate between spaced-apart source and drain regions. A control gate is then vertically aligned with the floating gate. Programming of the storage device is carried out by applying a potential to the control gate such that charge carriers are transported between the semiconductor substrate and the floating gate, whereupon the threshold voltage in the channel region established between the spaced-apart source and drain regions is modified. During read operations, the presence or absence of charge carriers on the floating gate can be determined by simply measuring the presence or absence of current flow through the channel region in response to voltage potentials applied to the drain region. When floating gate storage devices of the type described above are incorporated in a semiconductor memory array, individual floating gates are utilized for each storage device while a single conductive strip is etched to define the control gates for all of the storage devices in a single memory array row. This single conductive strip is commonly known as a word line. Similarly, the sources of all the storage devices in a memory array column are tied to a single conductive strip commonly known as a bit line. The drains of all the storage devices in the memory array column can either be grounded or tied to a second conductive strip running parallel to the bit line. The latter conductive strip is known as a write line and is used in conjunction with EEPROM storage devices such as those disclosed in co-pending application Ser. No. 343,847 filed Jan. 29, 1982.
The memory array is prepared for programming or read operations by enabling the word line of a particular memory array row using a unique x-address applied to the address inputs of the memory array and by simultaneously enabling the bit line of a particular memory array column using a unique y-address also applied to the memory array address inputs. Thereafter, charge carriers can be transported to the floating gate of the storage device located at the intersection of the enabled word and bit lines through application of the aforementioned programming potential to the enabled word line. Alternately, the presence or absence of charge carriers on the floating gate of the storage device can be determined by connecting the enabled bit line to a source of read potential and then sensing whether current flows along the bit line through the storage device channel region. Current flow, it will be recalled, indicates that charge carriers are not present on the floating gate whereas the absence of current flow indicates that charge carriers have been placed on the floating gate.
In order to determine whether current is flowing through an enabled bit line, and hence through a selected storage device connected to the enabled bit line, semiconductor memory arrays conventionally employ a sense amplifier to detect changes in bit line voltage and/or current levels. Although a variety of sense amplifier schemes may be utilized for this purpose, all such schemes are subject to several constraints. Specifically, an individual storage device in an unprogrammed state draws a minimal amount of current, generally on the order of 5 .mu.a. Thus, the sense amplifier current source supplying the enabled bit line must be small enough to furnish the required current without overloading the individual storage device. On the other hand, the relatively large number of storage devices connected to the same bit line effectively places a cumulative capacitance of relatively large magnitude on the sense amplifier, which cumulative capacitance is progressively discharged as word lines associated with storage devices other than the selected storage device are enabled during memory array read operations. If the sense amplifier current source is to provide current flow on the enabled bit line within the time constraints of practical semiconductor memory operation, an additional source of relatively large potential capable of rapidly charging the enabled bit line prior to reading the selected storage device is required. It is accordingly necessary to strike a balance between the competing demands of minimal current flow and rapid charge capacity when designing a sense amplifier for use with a semiconductor memory array.